1. Field of the Invention
The present invention relates to a voltage level shifter, and more particularly, to a voltage level shifter operated at an adjustment voltage.
2. Description of the Related Art
In recent years, memory devices are being applied to a variety of fields such as personal computers, portable terminals, IC cards, etc., and further development continues rapidly. The memory device includes any suitable type of random access memory (RAM), such as dynamic RAM (DRAM), static RAM (SRAM), and pseudo static RAM (PSRAM). FIG. 1 shows a portion of a conventional memory device 10. The memory device 10 comprises a memory cell array 16 for storing data, wherein the memory cell array 16 comprises a plurality of memory cells 162. Referring to FIG. 1, each memory cell 162 comprises one or more memory elements in a region where word lines WL0, WL1, . . . , WLn cross bit lines BL. In a DRAM, each memory cell 162 comprises a transistor, which controls writing or reading data with respect to a capacitor according to a word line signal.
The memory device 10 further comprises a row decoder 12, a charge pump 18, and a word line driver 14. The charge pump 18 is configured for receiving a low supply voltage VL and for generating a boosted voltage VH. The row decoder 12 is configured for receiving an address (ADRS) signal and for generating a plurality of output signals to the word line driver 14. The word line driver 14 comprises a level shifter 142 and a driver 146. During a write operation, the level shifter 142 converts the output signal of the row decoder 12 into a signal at the level of the voltage VH, and the driver 146 applies the voltage VH to the corresponding word lines WL0, WL1, . . . , WLn.
FIG. 2 shows a block diagram of a high level shifter 20 disclosed in U.S. Pat. No. 7,362,158. The level shifter 20 includes a first transistor 21, a second transistor 22, a third transistor 23, a fourth transistor 24 and an inverter 25. The level shifter 20 receives an input signal Vin which has two voltage levels VCC and GND, and generates an output signal Vout which has two voltage levels VDD and GND, where VDD>VCC. When the input signal Vin=VCC, the fourth transistor 24 is turned on, pulling a voltage at node N1 low, and then the first transistor 21 is turned on. When the first transistor 21 is turned on, a voltage at node N2 increases so that the voltage at node N1 decreases rapidly. Subsequently, the output signal Vout increases to a high level that is substantially equal to the voltage VDD. However, the architecture in FIG. 2 suffers from a deficiency in that the voltage VDD is controlled by the charge pump 18 as shown in FIG. 1. Therefore, when the input signal Vin=VCC and the voltage VDD is ramped up from GND to VCC-Vth via the charge pump 18, where Vth is a threshold voltage of the first transistor 21, a parasitic PN junction between the P+ drain and N-well of the first transistor 21 may turn on. As a result, the voltage VDD may not be increased. To solve the above deficiency, a fifth transistor (not shown), whose gate is connected to the voltage VDD, is needed between the drain of the first transistor 21 and the drain of the second transistor 22, resulting in a significant increase in chip area.
FIG. 3 shows a block diagram of a conventional low-level shifter 30. The level shifter 30 includes a first transistor 31, a second transistor 32, a third transistor 33, a fourth transistor 34 and an inverter 35. The level shifter 30 receives an input signal Vin which has two voltage levels VH and GND, and generates an output signal Vout which has two voltage levels VCC and GND, where VH>VCC. The level shifter 30 suffers from a deficiency in that the input signal Vin<VCC−Vth. In this case, the first transistor 31 is turned on. The second transistor 32 is turned on because Vin>0, and thus the fourth transistor 34 is turned on. Since the first and fourth transistors 31 and 34 are turned on at the same time, a short current is produced, pulling the voltage VCC down, approximately close to GND. Because the voltage VH is generated according to the voltage VCC, the voltage VH may not be increased.
Accordingly, there is a need to provide a level shifter which can overcome the previously described deficiencies.